I encountered this error a lot recently when trying to compile a customized Verilog project for USRP N210 using Xilinx ISE 12.2. Here is one reason why this error might happen from my experience.
It seems ISE does not like it when you use indexed array items in module instance port. For example:
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reg [31:0] ram[0:127]; reg [6:0] addr; some_module m_inst ( .clock(clock), .input(ram[addr]), // other ports );
This will mostly probably cause the INTERNAL_ERROR.
The walk around is to use a dedicated wire for the port instead of a indexed array item.
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reg [31:0] ram[0:127]; reg [6:0] addr; wire [31:0] the_input = ram[addr]; some_module m_inst ( .clock(clock), .input(the_input), // other ports );
Apparently this is just one of the possible reasons that could cause the error, but definitely worth checking out if you're desperate after exhausting out other possibilities.